Interconnection technology is constantly challenged to satisfy the ever increasing requirements for high density and performance associated with ultra large scale integration semiconductor devices. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the R×C product, the more limiting the circuit speed. As integrated circuits become complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the performance of multi-level interconnects is dominated by interconnect capacitance at deep sub-micron regimes, e.g., less than about 0.12 micron. The rejection rate due to integrated circuits speed delays in sub-micron regimes has become a limiting factor in fabrication.
One way to increase the control speed of semiconductor circuitry is to reduce the resistance of a conductive pattern. Copper (Cu) is considered a viable alternative to aluminum (Al) for metallization patterns, particularly for interconnect systems having smaller dimensions. Cu has a lower bulk resistivity and potentially higher electromigration tolerance than Al. Both the lower bulk resistivity and higher electromigration tolerance improve circuit performance. A conventional approach to forming a Cu interconnection involves the use of damascene processing in which openings are formed in an interlayer dielectric (ILD) and then filled with Cu. Such damascene techniques typically include single as well as dual damascene techniques, the latter comprising forming a via opening in communication with a trench opening and simultaneously filling by metal deposition to form a via in communication with a metal line.
However, Cu is a mid-gap impurity in silicon and silicon dioxide. Accordingly, Cu diffusion through interlayer dielectrics, such as silicon dioxide, degrades the performance of the integrated circuit. A conventional approach to the diffusion problem comprises depositing a barrier material to encapsulate the Cu line. Typically diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and titanium tungsten (TiW) for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between the Cu and the ILD, but includes interfaces with other metals as well. In depositing Cu by electroless deposition or electroplating, a seedlayer is also typically deposited to catalyze electroless deposition or to carry electric current for electroplating. For electroplating, the seedlayer must be continuous. However, for electroless plating, very thin catalytic layers can be employed in the form of eyelets.
Conventional Cu interconnect methodology typically comprises planarizing after Cu deposition, as by chemical-mechanical polishing (CMP), such that the upper surfaces of the filled trenches are substantially coplanar with the upper surface of the ILD. Subsequently a capping layer, such as silicon nitride or silicon carbide, is deposited to complete encapsulation of the Cu inlaid metallization.
The dielectric constant (k) of materials currently employed in the manufacture of semiconductor devices for an interlayer dielectric (ILD) ranges from about 3.9 for dense silicon dioxide to over 8 for deposited silicon nitride. The value of the dielectric constant (k) expressed herein is based upon a value of one (1) for a vacuum. In an effort to reduce interconnect capacitance, dielectric materials with lower values of permitivity have been employed. The expression “low-k” material has evolved to characterize materials with a dielectric constant less than about 3.9, e.g., less than 3.5. Various low-k dielectric materials, rules as porous low-k dielectric materials, e.g., dielectric materials having a porosity of 1% to 70%, offer promise, for example, such as porous SiLK™ available from Dow Chemical, located in Midland, Mich., and JSR5108 or JSR5109 available from JSR, located in Japan.
In attempting to employ various low-k materials, particularly porous low-k dielectric materials in interconnect technology, as for a dielectric layer in damascene techniques, various issues arise. For example, upon forming an opening in a porous dielectric material, such as a single or dual damascene opening, the sidewalls defining the opening have exposed pores. Upon depositing a conventional barrier layer material, such as Ta and/or TaN, when implementing Cu interconnect technology, chemical vapor deposition (CVD) or atomic layer deposition (ALD) may be employed so that the barrier layer is deposited in a conformal manner. However, deposition precursors usually diffuse into such porous ILD materials and deposit metal in the pores throughout the ILD film, thereby causing leakage and capacitance degradation. This problem is particularly acute in porous films where the pores are completely interconnected. This problem may also occur when employing non-porous low-k materials in situations where the CVD or ALD precursors diffuse into the ILD material and are trapped, thereby causing leakage and capacitance degradation.
Accordingly, a need exists for methodology enabling the fabrication of semiconductor devices having reliable interconnects, based on low-k ILDs, with uniformly deposited barrier metal layers without barrier metal penetration and/or diffusion into the low-k ILDs. A particular need exists for methodology enabling the fabrication of such semiconductor devices having copper (Cu) or Cu alloy interconnects using low-k porous dielectric materials.